H8SLASH3021 datasheet(421/712 Pages) RENESAS

421 / 712 page

12. Smart Card Interface

Rev.2.00 Mar. 22, 2007 Page 397 of 684

REJ09B0352-0200

12.1.3

Pin Configuration

Table 12.1 shows the Smart Card interface pin configuration.

Table 12.1

Smart Card Interface Pins

Pin Name

Abbreviation

I/O

Function

Serial clock pin 0

SCK

Output

SCI

0 clock output

Receive data pin 0

RxD

Input

SCI

0 receive data input

Transmit data pin 0

TxD

Output

SCI

0 transmit data output

12.1.4

Table 12.2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR,

TDR, and RDR are the same as for the normal SCI function: see the register descriptions in

section 11, Serial Communication Interface.

Table 12.2

Smart Card Interface Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'FFB0

Serial mode register

SMR

R/W

H'00

H'FFB1

Bit rate register

BRR

R/W

H'FF

H'FFB2

Serial control register

SCR

R/W

H'00

H'FFB3

Transmit data register

TDR

R/W

H'FF

H'FFB4

Serial status register

SSR

R/(W)*

H'84

H'FFB5

Receive data register

RDR

H'00

H'FFB6

Smart card mode

SCMR

R/W

H'F2

Notes: 1. Lower 16 bits of the address.

2. Can only be written with 0 for flag clearing.

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