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H8/3021 Datasheet(PDF) 648 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 648 Page - Renesas Technology Corp |
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648 / 712 page ![]() Appendix B. Internal I/O Register Field Rev.2.00 Mar. 22, 2007 Page 624 of 684 REJ09B0352-0200 NDERB—Next Data Enable Register B H'A2 TPC Bit Initial value Read/Write 7 NDER15 0 R/W 6 NDER14 0 R/W 5 NDER13 0 R/W 4 NDER12 0 R/W 3 NDER11 0 R/W 0 NDER8 0 R/W 2 NDER10 0 R/W 1 NDER9 0 R/W Next data enable 15 to 8 TPC outputs TP to TP * are disabled (NDR15 to NDR8 are not transferred to PB to PB ) TPC outputs TP to TP * are enabled (NDR15 to NDR8 are transferred to PB to PB ) Bits 7 to 0 0 1 Description Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip. NDER15 to NDER8 15 15 8 8 7 7 0 0 NDERA—Next Data Enable Register A H'A3 TPC Bit Initial value Read/Write 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 0 NDER0 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W Next data enable 7 to 0 TPC outputs TP to TP are disabled (NDR7 to NDR0 are not transferred to PA to PA ) TPC outputs TP to TP are enabled (NDR7 to NDR0 are transferred to PA to PA ) Bits 7 to 0 0 1 Description NDER7 to NDER0 7 7 0 0 7 7 0 0 |
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