H8SLASH3021 datasheet(113/712 Pages) RENESAS

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5. Interrupt Controller

Rev.2.00 Mar. 22, 2007 Page 89 of 684

REJ09B0352-0200

5.2.3

IRQ Status Register (ISR)

ISR is an 8-bit readable/writable register that indicates the status of IRQ

0, IRQ1, IRQ4, and IRQ5

interrupt requests.

Bit

Initial value

Read/Write

—

These bits indicate IRQ5 and IRQ4

interrupt request status

Note:

Only 0 can be written, to clear flags.

—

IRQ5F

R/(W)*

IRQ4F

R/(W) *

—

IRQ1F

R/(W) *

IRQ0F

R/(W) *

IRQ to IRQ flags

These bits indicates IRQ1 and IRQ0

interrupt request status

IRQ , IRQ

flags

Reserved bits

ISR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7, 6, 3 and 2—Reserved: These bits cannot be modified and are always read as 0.

Bits 5, 4, 1 and 0—IRQ

5, IRQ4, IRQ1 and IRQ0 Flags (IRQ5F, IRQ4F, IRQ1F, and IRQ0F):

These bits indicate the status of IRQ

5, IRQ4, IRQ1 and IRQ0 interrupt requests.

Bits 5, 4, 1, and 0

IRQ5F, IRQ4F, IRQ1F,

and IRQ0F

Description

[Clearing conditions]

(Initial value)

0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.

IRQnSC = 0,

IRQn input is high, and interrupt exception handling is

carried out.

IRQnSC = 1 and IRQn interrupt exception handling is carried out.

[Setting conditions]

IRQnSC = 0 and

IRQn input is low.

IRQnSC = 1 and

IRQn input changes from high to low.

Note: n = 5, 4, 1 and 0

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