H8SLASH3021 datasheet(170/712 Pages) RENESAS

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7. I/O Ports

Rev.2.00 Mar. 22, 2007 Page 146 of 684

REJ09B0352-0200

7.5

Port 5

7.5.1

Overview

Port 5 is a 4-bit input/output port with the pin configuration shown in figure 7.12. The pin

functions differ depending on the operating mode.

In modes 1, 3 (expanded modes with on-chip ROM disabled), port 5 consists of address output

pins (A

19 to A16). In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings in the

port 5 data direction register (P5DDR) designate pins for address bus output (A

19 to A16) or generic

input. In mode 7 (single-chip mode), port 5 is a generic input/output port.

Port 5 has software-programmable built-in pull-up transistors. Port 5 can drive one TTL load and a

90-pF capacitive load. They can also drive an LED or a Darlington transistor pair.

Port 5

P5 /A

(output)

P5 (input)/A

(output)

P5 (input)/A

(output)

P5 (input)/A

(output)

P5 (input)/A

(output)

Port 5

pins

Modes 1, 3

Modes 5 and 6

P5 (input/output)

Mode 7

Figure 7.12 Port 5 Pin Configuration

7.5.2

Table 7.6 summarizes the registers of port 5.

Table 7.6

Port 5 Registers

Initial Value

Address*

Name

Abbreviation

R/W

Modes 1 and 3

Modes 5 to 7

H'FFC8

Port 5 data

direction register

P5DDR

H'FF

H'F0

H'FFCA

Port 5 data

P5DR

R/W

H'F0

H'FFDB

Port 5 input pull-up

control register

P5PCR

R/W

H'F0

Note:

Lower 16 bits of the address.

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