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H8/3021 Datasheet(PDF) 192 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 192 Page - Renesas Technology Corp |
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192 / 712 page  7. I/O Ports Rev.2.00 Mar. 22, 2007 Page 168 of 684 REJ09B0352-0200 Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for pins PA 7 to PA0. Bit Initial value Read/Write 0 PA 0 R/W 0 1 PA 0 R/W 1 2 PA 0 R/W 2 3 PA 0 R/W 3 4 PA 0 R/W 4 5 PA 0 R/W 5 6 PA 0 R/W 6 7 PA 0 R/W 7 Port A data 7 to 0 These bits store data for port A pins When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read. PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. When port A pins are used for TPC output, PADR stores output data for TPC output groups 0 and 1. If a bit in the next data enable register (NDERA) is set to 1, the corresponding PADR bit cannot be written. In this case, PADR can be updated only when data is transferred from NDRA. |
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