H8SLASH3021 datasheet(201/712 Pages) RENESAS

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7. I/O Ports

Rev.2.00 Mar. 22, 2007 Page 177 of 684

REJ09B0352-0200

Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select

input or output for each pin in port B.

Bit

Initial value

Read/Write

PB DDR

These bits select input or output for port B pins

—

PB DDR

Port B data 7, 5 to 0

Reserved bit

A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin

if this bit is cleared to 0.

Bit 6 is reserved.

PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.

PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting. If a PBDDR bit is set to 1, the corresponding pin maintains its output

state in software standby mode.

Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores data for

pins PB

7, PB5 to PB0.

Bit

Initial value

Read/Write

R/W

—

R/W

Port B data 7, 5 to 0

These bits store data for port B pins

Reserved bit

When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is

returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin

level is read. Bit 6 is reserved. Bit 6 can be written and read, but cannot be used for a port input or

output.

If bit 6 in PBDDR is read while its value is 1, the value of bit 6 in PBDR will be read directly. If

bit 6 in PBDDR is read while its value is 0, it will always be read as 1.

H8/3021 Datasheet(PDF) 201 Page - Renesas Technology Corp