 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
H8/3021 Datasheet(PDF) 302 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8/3021 Datasheet(HTML) 302 Page - Renesas Technology Corp |
|
|
302 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 278 of 684 REJ09B0352-0200 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T 3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8.68. φ Address Internal write signal Input capture signal TCNT GR M GR address General register write cycle T1 T2 T3 M Figure 8.68 Contention between General Register Write and Input Capture Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: φ f = (N + 1) (f: counter frequency. φ: system clock frequency. N: value set in general register.) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
