H8SLASH3028F datasheet(348/923 Pages) RENESAS

348 / 923 page

Rev. 2.00, 09/03, page 318 of 890

Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or

synchronously.

Bit 1

SYNC1

Description

Channel 1’s timer counter (16TCNT1) operates independently

(Initial value)

16TCNT1 is preset and cleared independently of other channels

Channel 1 operates synchronously

16TCNT1 can be synchronously preset and cleared

Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or

synchronously.

Bit 0

SYNC0

Description

Channel 0’s timer counter (16TCNT0) operates independently

(Initial value)

16TCNT0 is preset and cleared independently of other channels

Channel 0 operates synchronously

16TCNT0 can be synchronously preset and cleared

9.2.3

Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also

selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.

Bit

Initial value

Read/Write

—

MDF

R/W

FDIR

R/W

—

PWM0

R/W

PWM2

R/W

PWM1

R/W

Reserved bit

PWM mode 2 to 0

These bits select PWM

mode for channels 2 to 0

Phase counting mode flag

Selects phase counting mode for channel 2

Flag direction

Selects the setting condition for the overflow

flag (OVF) in TISRC

TMDR is initialized to H'98 by a reset and in standby mode.

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