H8SLASH3028F datasheet(372/923 Pages) RENESAS

372 / 923 page

Rev. 2.00, 09/03, page 342 of 890

• Free-running and periodic counter operation

A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running

counters. A free-running counter starts counting up when the corresponding bit in TSTR is set

to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.

After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates

free-running counting.

16TCNT value

H'FFFF

H'0000

STR0 to

STR2 bit

OVF

Time

Figure 9.13 Free-Running Counter Operation

When a channel is set to have its counter cleared by compare match, in that channel 16TCNT

operates as a periodic counter. Select the output compare function of GRA or GRB, set bit

CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count

period in GRA or GRB. After these settings, the counter starts counting up as a periodic

counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or

GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to

H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU

interrupt is requested at this time. After the compare match, 16TCNT continues counting up

from H'0000. Figure 9.14 illustrates periodic counting.

16TCNT value

H'0000

STR bit

IMF

Time

Counter cleared by general

Figure 9.14 Periodic Counter Operation

H8/3028F Datasheet(PDF) 372 Page - Renesas Technology Corp