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H8/3028F Datasheet(PDF) 389 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 389 Page - Renesas Technology Corp |
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389 / 923 page ![]() Rev. 2.00, 09/03, page 359 of 890 Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing. Overflow signal 16TCNT φ OVF OVI Figure 9.35 Timing of Setting of OVF 9.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 9.36 shows the timing. φ Address IMF, OVF TISR write cycle TISR address T1 T2 T3 Figure 9.36 Timing of Clearing of Status Flags |
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