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H8/3028F Datasheet(PDF) 391 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 391 Page - Renesas Technology Corp |
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391 / 923 page ![]() Rev. 2.00, 09/03, page 361 of 890 9.6 Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T3 state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 9.37. φ Address bus Internal write signal Counter clear signal 16TCNT 16TCNT write cycle 16TCNT address N H'0000 T1 T2 T3 Figure 9.37 Contention between 16TCNT Write and Clear |
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