H8SLASH3028F datasheet(411/923 Pages) RENESAS

411 / 923 page

Rev. 2.00, 09/03, page 381 of 890

10.2.4

Timer Control Register (8TCR)

CMIEB

R/W

CMIEA

R/W

OVIE

R/W

CCLR1

R/W

CCLR0

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT

clearing specification, and enables interrupt requests.

8TCR is initialized to H'00 by a reset and in standby mode.

For the timing, see section 10.4, Operation.

Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt

request when the CMFB flag is set to 1 in 8TCSR.

Bit 7

CMIEB

Description

CMIB interrupt requested by CMFB is disabled

(Initial value)

CMIB interrupt requested by CMFB is enabled

Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt

request when the CMFA flag is set to 1 in 8TCSR.

Bit 6

CMIEA

Description

CMIA interrupt requested by CMFA is disabled

(Initial value)

CMIA interrupt requested by CMFA is enabled

Bit 5—Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt

request when the OVF flag is set to 1 in 8TCSR.

Bit 5

OVIE

Description

OVI interrupt requested by OVF is disabled

(Initial value)

OVI interrupt requested by OVF is enabled

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