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H8/3028F Datasheet(PDF) 414 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 414 Page - Renesas Technology Corp |
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414 / 923 page ![]() Rev. 2.00, 09/03, page 384 of 890 10.2.5 Timer Control/Status Registers (8TCSR) 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 — 1 — 3 OIS3 0 R/W 0 OS0 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 8TCSR2 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 0 R/W 3 OIS3 0 R/W 0 OS0 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 8TCSR0 ADTE Bit Initial value Read/Write Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICE 0 R/W 3 OIS3 0 R/W 0 OS0 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 8TCSR1, 8TCSR3 Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Bit Initial value Read/Write The timer control/status registers 8TCSR are 8-bit registers that indicate compare match/input capture and overflow statuses, and control compare match output/input capture edge selection. 8TCSR2 is initialized to H'10, and 8TCSR0, 8TCSR1, and 8TCSR3 to H'00, by a reset and in standby mode. |
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