H8SLASH3028F datasheet(514/923 Pages) RENESAS

514 / 923 page

Rev. 2.00, 09/03, page 484 of 890

Clock

An internal clock generated by the on-chip baud rate generator or an external clock input from the

SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the

A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see

table 13.9.

When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit

rate.

When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The

frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 13.3

so that the rising edge of the clock occurs at the center of each transmit data bit.

0/1

frame

Figure 13.3 Phase Relationship between Output Clock and Serial Data

(Asynchronous Mode)

Transmitting and Receiving Data

SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE and

RE bits to 0 in SCR, then initialize the SCI as follows.

When changing the communication mode or format, always clear the TE and RE bits to 0 before

following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes

TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags, or

RDR, which retain their previous contents.

When an external clock is used the clock should not be stopped during initialization or subsequent

operation, since operation will be unreliable in this case.

H8/3028F Datasheet(PDF) 514 Page - Renesas Technology Corp