H8SLASH3028F datasheet(555/923 Pages) RENESAS

555 / 923 page

Rev. 2.00, 09/03, page 525 of 890

14.3.5

Clock

Only an internal clock generated by the on-chip baud rate generator can be used as the

transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register

(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for

calculating the bit rate is shown below. Table 14.5 shows some sample bit rates.

If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is

output from the SCK pin.

B =

1488

× 22n–1 × (N + 1)

× 106

where, N: BRR setting (0

≤ N ≤ 255)

B: Bit rate (bit/s)

φ: Operating frequency (MHz)

n: See table 14.4

Table 14.4 n-Values of CKS1 and CKS0 Settings

CKS1

CKS0

Note: If the gear function is used to divide the clock frequency, use the divided frequency to

calculate the bit rate. The equation above applies directly to 1/1 frequency division.

Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)

φφφφ (MHz)

7.1424

10.00

10.7136

13.00

14.2848

16.00

18.00

20.00

25.00

9600.0

13440.9

14400.0

17473.1

19200.0

21505.4

24193.5

26881.7

33602.2

4800.0

6720.4

7200.0

8736.6

9600.0

10752.7

12096.8

13440.9

16801.1

3200.0

4480.3

4800.0

5824.4

6400.0

7168.5

8064.5

8960.6

11200.7

Note: Bit rates are rounded off to one decimal place.

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