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H8/3028F Datasheet(PDF) 556 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 556 Page - Renesas Technology Corp |
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556 / 923 page  Rev. 2.00, 09/03, page 526 of 890 The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. N = 1488 × 22n–1 × B × 106 – 1 φ Table 14.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0) φφφφ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.00 bit/s N Error N Error N Error N Error N Error N Error N Error N Error N Error 9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.66 3 12.49 Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode) φφφφ (MHz) Maximum Bit Rate (bits/s) N n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 25.00 33602 0 0 The bit rate error is given by the following equation: Error (%) = 1488 × 22n-1 × B × (N + 1) × 106 – 1 × 100 φ |
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