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H8/3028F Datasheet(PDF) 577 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 577 Page - Renesas Technology Corp |
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577 / 923 page  Rev. 2.00, 09/03, page 547 of 890 15.2.3 A/D Control Register (ADCR) Bit Initial value Read/Write 7 TRGE 0 R/W 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 0 — 0 R/W 2 — 1 — 1 — 1 — Trigger enable Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match Reserved bits ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match. Bit 7 TRGE Description 0 Starting of A/D conversion by an external trigger or 8-bit timer compare match is disabled (Initial value) 1 A/D conversion is started at the falling edge of the external trigger signal ( ADTRG) or by an 8-bit timer compare match External trigger pin and 8-bit timer selection are performed by the 8-bit timer. For details, see section 10, 8-Bit Timers. Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 1. Bit 0—Reserved: This bit can be read or written, but must not be set to 1. |
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