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H8/3028F Datasheet(PDF) 578 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 578 Page - Renesas Technology Corp |
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578 / 923 page  Rev. 2.00, 09/03, page 548 of 890 15.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15.2 shows the data flow for access to an A/D data register. Upper-byte read Bus interface Module data bus CPU (H'AA) ADDRnH (H'AA) ADDRnL (H'40) Lower-byte read Bus interface Module data bus CPU (H'40) ADDRnH (H'AA) ADDRnL (H'40) TEMP (H'40) TEMP (H'40) (n = A to D) (n = A to D) Figure 15.2 A/D Data Register Access Operation (Reading H'AA40) |
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