H8SLASH3028F datasheet(810/923 Pages) RENESAS

810 / 923 page

Rev. 2.00, 09/03, page 780 of 890

DTCR0A—Data Transfer Control Register 0A

H'FFF27

DMAC0

• Short address mode

Bit

Initial value

Read/Write

R/W

DTE

R/W

DTSZ

R/W

DTID

R/W

RPE

R/W

DTIE

R/W

DTS2

R/W

DTS1

R/W

DTS0

Data transfer size

Byte-size transfer

Word-size transfer

Data transfer increment/decrement

Incremented:

If DTSZ = 0, MAR is incremented by 1 after each transfer

If DTSZ = 1, MAR is incremented by 2 after each transfer

Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer

If DTSZ = 1, MAR is decremented by 2 after each transfer

Data transfer enable

Data transfer is disabled

Data transfer is enabled

Data transfer select

Bit 2

DTS2

Bit 1

DTS1

Bit 0

DTS0

Compare match/input capture A

interrupt from 16-bit timer channel 0

Compare match/input capture A

interrupt from 16-bit timer channel 1

Compare match/input capture A

interrupt from 16-bit timer channel 2

A/D converter conversion end interrupt

SCI0 transmit-data-empty interrupt

SCI0 receive-data-full interrupt

Transfer in full address mode

Data Transfer Activation Source

Repeat enable

RPE

DTIE

I/O mode

Repeat mode

Idle mode

Description

Data transfer interrupt enable

Interrupt requested by DTE bit is disabled

Interrupt requested by DTE bit is enabled

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