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H8/3028F Datasheet(PDF) 806 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 806 Page - Renesas Technology Corp |
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806 / 923 page ![]() Rev. 2.00, 09/03, page 776 of 890 RAMCR—RAM Control Register H'EE077 Flash Memory Bit 3 Bit 2 Bit 1 Bit 0 RAMS RAM2 RAM1 RAM0 RAM Area 0/1 0 1 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 RAM Emulation Status H'FFE000 to H'FFEFFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Emulation Mapping RAM RAM select, RAM2 to RAM0 Bit 7 — RAMS 65 4 3 2 1 0 ——— RAM2 RAM1 RAM0 Reserved bits Modes 1 to 4 1 — 1 — 1 — 1 — 0 R 0 R 0 R 0 — Initial value R/W Initial value R/W Modes 5 to 7 1 — 1 — 1 — 1 — 0 R/W * 0 R/W * 0 R/W * 0 R/W * * In mode 6 (single-chip normal mode), flash memory emulation by RAM is not supported; these bits can be modified, but must not be set to 1. Notes: This register is used only in the flash memory and flash memory R versions. Reading the corresponding address in a mask ROM version will always return 1s, and writes to this address are disabled. |
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