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H8/3028F Datasheet(PDF) 114 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 114 Page - Renesas Technology Corp |
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114 / 923 page  Rev. 2.00, 09/03, page 84 of 890 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 0 RAME 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W Software standby Standby timer select 2 to 0 User bit enable Selects whether to use the UI bit in CCR as a user bit or interrupt mask bit NMI edge select Selects the NMI input edge Software standby output port enable RAM enable Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge. Bit 2 NMIEG Description 0 Interrupt is requested at falling edge of NMI input (Initial value) 1 Interrupt is requested at rising edge of NMI input 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. |
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