H8SLASH3028F datasheet(147/923 Pages) RENESAS

147 / 923 page

Rev. 2.00, 09/03, page 117 of 890

6.2.4

Bus Release Control Register (BRCR)

BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A20 and

enables or disables release of the bus to an external device.

A23E

—

R/W

Address 23 to 20 enable

These bits enable PA7 to PA4 to be

used for A23 to A20 address output

A22E

—

R/W

A21E

—

R/W

A20E

—

R/W

—

BRLE

R/W

Bit

Modes

1, 2, 6,

and 7

Initial value

Read/Write

Initial value

Read/Write

Initial value

Read/Write

Modes

3 and 4

Mode 5

Reserved bits

Bus release enable

Enables or disables

release of the bus

to an external device

BRCR is initialized to H'FE in modes 1, 2, 5, 6, and 7, and to H'EE in modes 3 and 4, by a reset

and in hardware standby mode. It is not initialized in software standby mode.

Bit 7—Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin.

Writing 0 in this bit enables A23 output from PA4. In modes other than 3, 4, and 5, this bit cannot

be modified and PA4 has its ordinary port functions.

Bit 7

A23E

Description

0PA4 is the A23 address output pin

1PA4 is an input/output pin

(Initial value)

Bit 6—Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin.

Writing 0 in this bit enables A22 output from PA5. In modes other than 3, 4, and 5, this bit cannot

be modified and PA5 has its ordinary port functions.

Bit 6

A22E

Description

0PA5 is the A22 address output pin

1PA5 is an input/output pin

(Initial value)

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