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H8/3028F Datasheet(PDF) 148 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 148 Page - Renesas Technology Corp |
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148 / 923 page  Rev. 2.00, 09/03, page 118 of 890 Bit 5—Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin. Writing 0 in this bit enables A21 output from PA6. In modes other than 3, 4, and 5, this bit cannot be modified and PA6 has its ordinary port functions. Bit 5 A21E Description 0PA6 is the A21 address output pin 1PA6 is an input/output pin (Initial value) Bit 4—Address 20 Enable (A20E): Enables PA7 to be used as the A20 address output pin. Writing 0 in this bit enables A20 output from PA7. This bit can only be modified in mode 5. Bit 4 A20E Description 0PA7 is the A20 address output pin (Initial value when in mode 3 or 4) 1PA7 is an input/output pin (Initial value when in mode 1, 2, 5, 6 or 7) Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1. Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device. Bit 0 BRLE Description 0 The bus cannot be released to an external device BREQ and BACK can be used as input/output pins (Initial value) 1 The bus can be released to an external device 6.2.5 Bus Control Register (BCR) BRSTS0 EMC RDEA WAITE 1 Initial value 1 0 0 0 1 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 765 4 3 210 ICIS1 ICIS0 BROME BRSTS1 Bit BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the address map, selects the area division unit, and enables or disables WAIT pin input. BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in software standby mode. |
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