H8SLASH3028F datasheet(233/923 Pages) RENESAS

233 / 923 page

Rev. 2.00, 09/03, page 203 of 890

7.3.4

Data Transfer Control Registers (DTCR)

The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the

operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and

DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address

mode.

DTCRA

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

SAID

R/W

SAIDE

R/W

DTIE

R/W

DTS0A

R/W

DTS2A

R/W

DTS1A

R/W

Data transfer enable

Enables or disables

data transfer

Enables or disables the

CPU interrupt at the end

of the transfer

Data transfer size

Selects byte or

word size

Source address

increment/decrement

Data transfer select

2A and 1A

These bits must both be

set to 1

Data transfer

interrupt enable

Source address increment/

decrement enable

These bits select whether

the source address register

(MARA) is incremented,

decremented, or held fixed

during the data transfer

Selects block

transfer mode

Data transfer

select 0A

DTCRA is initialized to H'00 by a reset and in standby mode.

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