H8SLASH3028F datasheet(236/923 Pages) RENESAS

236 / 923 page

Rev. 2.00, 09/03, page 206 of 890

DTCRB

Bit

Initial value

Read/Write

DTME

R/W

—

R/W

DAID

R/W

DAIDE

R/W

TMS

R/W

DTS0B

R/W

DTS2B

R/W

DTS1B

R/W

Data transfer master enable

Enables or disables data

transfer, together with

the DTE bit, and is cleared

to 0 by an interrupt

Reserved bit

Destination address

increment/decrement

Data transfer select

2B to 0B

These bits select the data

transfer activation source

Transfer mode select

Destination address

increment/decrement enable

These bits select whether

the destination address

decremented, or held fixed

during the data transfer

Selects whether the

block area is the source

or destination in block

transfer mode

DTCRB is initialized to H'00 by a reset and in standby mode.

Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit

enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is

enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the

CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further

information on operation in block transfer mode, see section 7.6.6, NMI Interrupts and Block

Transfer Mode.

DTME is set to 1 by reading the register while DTME = 0, then writing 1.

Bit 7

DTME

Description

Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt

(Initial value)

occurs)

Data transfer is enabled

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