H8SLASH3028F datasheet(239/923 Pages) RENESAS

239 / 923 page

Rev. 2.00, 09/03, page 209 of 890

7.4

Operation

7.4.1

Overview

Table 7.5 summarizes the DMAC modes.

Table 7.5

DMAC Modes

Transfer Mode

Activation

Notes

Compare match/input

capture A interrupt from

16-bit timer channels 0 to 2

Transmit-data-empty

and receive-data-full

interrupts from SCI

channel 0

Conversion-end interrupt

from A/D converter

Short address

mode

I/O mode

Idle mode

Repeat mode

External request

• Up to four channels

can operate independently

• Only the B channels

support external requests

Auto-request

Normal mode

External request

Compare match/input

capture A interrupt from

16-bit timer channels 0 to 2

Conversion-end interrupt

from A/D converter

Full address

mode

Block transfer

mode

External request

• A and B channels are

paired; up to two channels

are available

• Burst mode transfer or

cycle-steal mode transfer

can be selected for auto-

requests

A summary of operations in these modes follows.

I/O Mode: One byte or word is transferred per request. A designated number of these transfers are

executed. A CPU interrupt can be requested at completion of the designated number of transfers.

One 24-bit address and one 8-bit address are specified. The transfer direction is determined

automatically from the activation source.

Idle Mode: One byte or word is transferred per request. A designated number of these transfers

are executed. A CPU interrupt can be requested at completion of the designated number of

transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The

transfer direction is determined automatically from the activation source.

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