H8SLASH3002 datasheet(85/700 Pages) RENESAS

85 / 700 page

4.3 Interrupts

Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5) and

30 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources

and indicates the number of interrupts of each type.

The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),

refresh controller, 16-bit integrated timer-pulse unit (ITU), DMA controller (DMAC), serial

communication interface (SCI), and A/D converter. Each interrupt source has a separate vector

address.

NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the

interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority

levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt

priority registers A and B (IPRA and IPRB) in the interrupt controller.

For details on interrupts see section 5, Interrupt Controller.

Figure 4-4 Interrupt Sources and Number of Interrupts

Interrupts

External interrupts

Internal interrupts

NMI (1)

IRQ to IRQ (6)

WDT

(1)

Refresh controller

(1)

ITU (15)

DMAC (4)

SCI (8)

A/D converter (1)

Notes: Numbers in parentheses are the number of interrupt sources.

When the watchdog timer is used as an interval timer, it generates an interrupt

request at every counter overflow.

When the refresh controller is used as an interval timer, it generates an interrupt

request at compare match.

H8/3002 Datasheet(PDF) 85 Page - Renesas Technology Corp