H8SLASH3002 datasheet(28/700 Pages) RENESAS

28 / 700 page

Table 1-3 Pin Functions (cont)

Pin No.

FP-100B,

Type

Symbol

TFP-100B

FP-100A

I/O

Name and Function

System

RES

Input

Reset input: When driven low, this pin

control

resets control the H8/3002

RESO

Output

Reset output: Outputs the reset signal

generated by the watchdog timer to external

devices.

STBY

Input

Standby: When driven low, this pin forces a

transition to hardware standby mode

BREQ

Input

Bus request: Used by an external bus

master to request the bus right from the

H8/3002

BACK

Output

Bus request acknowledge: Indicates that

the bus has been granted to an external bus

master

Interrupts

NMI

Input

Nonmaskable interrupt: Requests a

nonmaskable interrupt

IRQ5 to

17, 16,

19, 18

Input

Interrupt request 5 to 0: Maskable

IRQ0

90 to 87

92 to 89

interrupt request pins

Address

Modes

A19 to 56 to 45,

58 to 47

Output

Address bus: Outputs address signals

bus

1 and 2 A0

43 to 36

45 to38

Modes

A23 to 100 to 97,

99, 100,

3 and 4 A0

56 to 45,

1, 2,

43 to 36

58 to 47

45 to 38

Data bus

D15 to D0

34 to 23,

36 to 25

Input/

Data bus: Bidirectional data bus

21 to 18

23 to 20

output

Bus control

CS3 to CS0

91 to 88

90 to 93

Output

Chip select: Select signals for areas 3 to 0

Output

Address strobe: Goes low to indicate valid

address output on the address bus

Output

Read: Goes low to indicate reading from the

external address space

HWR

Output

High write: Goes low to indicate writing to

the external address space; indicates valid

data on the upper data bus (D15 to D8).

LWR

Output

Low write: Goes low to indicate writing to

the external address space; indicates valid

data on the lower data bus (D7 to D0).

WAIT

Input

Wait: Requests insertion of wait states in

bus cycles during access to the external

address space

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