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H8/3002 Datasheet(PDF) 294 Page - Renesas Technology Corp |
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H8/3002 Datasheet(HTML) 294 Page - Renesas Technology Corp |
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294 / 700 page  10.1.2 Block Diagrams ITU Block Diagram (Overall): Figure 10-1 is a block diagram of the ITU. Figure 10-1 ITU Block Diagram (Overall) Module data bus IMIA0 to IMIA4 IMIB0 to IMIB4 OVI0 to OVI4 TCLKA to TCLKD ø, ø/2, ø/4, ø/8 TOCXA4, TOCXB4 Clock selector Control logic TIOCA0 to TIOCA4 TIOCB0 to TIOCB4 TOER TOCR TSTR TSNC TMDR TFCR TOER: TOCR: TSTR: TSNC: TMDR: TFCR: Legend Timer output master enable register (8 bits) Timer output control register (8 bits) Timer start register (8 bits) Timer synchro register (8 bits) Timer mode register (8 bits) Timer function control register (8 bits) 280 |
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