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LTC2301CDEXPBF Datasheet(PDF) 17 Page - Linear Technology |
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LTC2301CDEXPBF Datasheet(HTML) 17 Page - Linear Technology |
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17 / 24 page  LTC2301/LTC2305 17 23015f APPLICATIONS INFORMATION Output Data Format The output register contains the last conversion result. After each conversion is completed, the device automati- cally enters either nap or sleep mode depending on the setting of the SLP bit (see Nap Mode and Sleep Mode sections). When the LTC2301/LTC2305 is addressed for a read operation, it acknowledges by pulling SDA low and acts as a transmitter. The master/receiver can read up to two bytes from the LTC2301/LTC2305. After a complete read operation of 2 bytes, a Stop condition is needed to initiate a new conversion. The device will NAK subsequent read operations while a conversion is being performed. The data output stream is 16 bits long and is shifted out on the falling edges of SCL (see Figure 7a). The first bit is the MSB and the 12th bit is the LSB of the conversion result. The remaining four bits are zero. Figures 13 and 14 are the transfer characteristics for the bipolar and unipolar modes. Data is output on the SDA line in 2’s complement format for bipolar readings and in straight binary for unipolar readings. Input Data Format When the LTC2301/LTC2305 is addressed for a write operation, it acknowledges by pulling SDA low during the low period before the 9th cycle and acts as a receiver. The master/transmitter can then send 1 byte to program the device. The input byte consists of the 6-bit DIN word followed by two bits that are ignored by the ADC and are considered don’t cares (X) (see Figure 7b). The input bits are latched on the rising edge of SCL during the write operation. Figure 7a. Timing Diagram for Reading from the LTC2301/LTC2305 12 A6 SDA START BY MASTER ACK BY ADC ACK BY MASTER NAK BY MASTER STOP BY MASTER CONVERSION INITIATED SCL SCL (CONTINUED) A5 A4 A3 A2 A1 A0 R/W 3456789 123456789 123456789 23015 F07a B11 B10 READ 1 BYTE B9 B8 B7 MOST SIGNIFICANT DATA BYTE B6 B5 B4 • • • • • • SDA (CONTINUED) • • • • • • B3 B2 B1 B0 LEAST SIGNIFICANT DATA BYTE READ 1 BYTE ADDRESS FRAME Figure 7b. Timing Diagram for Writing to the LTC2301/LTC2305 12 A6 SDA START BY MASTER ACK BY ADC ACK BY ADC CONVERSION INITIATED STOP BY MASTER SCL A5 A4 A3 A2 A1 A0 R/W 3456789 123456789 23015 F07b S/D O/S WRITE 1 BYTE X X UNI DIN WORD SLP X X ADDRESS FRAME NOTE: S/D BIT IS A DON’T CARE (X) FOR THE LTC2301 |
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