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LTC2301/LTC2305

23015f

APPLICATIONS INFORMATION

Sleep Mode

The ADCs enter sleep mode after a conversion is complete

(tCONV) if the SLP bit is set to a logic 1. The ADCs draw

only 7μA in sleep mode, provided that none of the digital

inputs are switching. When the LTC2301/LTC2305 are

properly addressed, the ADCs are released from sleep

mode and require 200ms (tREFWAKE) to wake up and charge

the respective 2.2μF and 10μF bypass capacitors on the

VREF and REFCOMP pins. A new conversion should not

be initiated before this time as shown in Figure 11.

Acquisition

The LTC2301/LTC2305 begin acquiring the input signal at

different instances depending on whether a read or write

operation is being performed. If a read operation is being

performed, acquisition of the input signal begins on the

rising edge of the 9th clock pulse following the address

frame as shown in Figure 12a.

If a write operation is being performed, acquisition of the

input signal begins on the falling edge of the sixth clock

cycle after the DIN word has been shifted in as shown in

Figure 12b. The LTC2301/LTC2305 will acquire the signal

from the input channel that was most recently programmed

by the DIN word. A minimum of 240ns is required to acquire

the input signal before initiating a new conversion.

Board Layout and Bypassing

To obtain the best performance, a printed circuit board with

a solid ground plane is required. Layout for the printed

board should ensure digital and analog signal lines are

CONVERSION

SLEEP

tREFWAKE

CONVERSION

R/W

ACK

7-BIT ADDRESS

23015 F11

Figure 11. Exiting Sleep Mode and Starting a New Conversion

Figure 12a. Timing Diagram Showing Acquisition During a Read Operation

SDA

SCL

R/W

3456789

B11

ACQUISITION BEGINS

tACQ

23015 F12a

B10

Figure 12b. Timing Diagram Showing Acquisition During a Write Operation

R/W

SDA

SCL

S/D

O/S

UNI

345

56789

6789

ACQUISITION BEGINS

tACQ

23015 F12b

SLP

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