AT89C51AC3-RDTIM datasheet(63/140 Pages) ATMEL

63 / 140 page

AT89C51AC3

4383D–8051–02/08

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send an address FFh. To communicate with slaves A

and B, but not slave C, the master can send and address FBh.

Registers

Table 25. SCON Register

SCON (S:98h)

Serial Control Register

Reset Value = 0000 0000b

Bit addressable

FE/SM0

SM1

SM2

REN

TB8

RB8

Bit

Number

Bit

Mnemonic Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

SM0

Serial port Mode bit 0 (SMOD0=0)

Refer to SM1 for serial port mode selection.

SM1

Serial port Mode bit 1

SM0

SM1

Mode

Baud Rate

Shift Register F

XTAL/12 (or FXTAL /6 in mode X2)

8-bit UART

Variable

9-bit UART

XTAL/64 or FXTAL/32

9-bit UART

Variable

SM2

Serial port Mode 2 bit/Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3.

REN

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

TB8

Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

RB8

Receiver Bit 8/Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the

stop bit in the other modes.

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 33. and

Figure 34. in the other modes.

AT89C51AC3-RDTIM Datasheet(PDF) 63 Page - ATMEL Corporation

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