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A32100DX-FPLC Datasheet(PDF) 28 Page - Actel Corporation

Part # A32100DX-FPLC
Description  Integrator Series FPGAs: 1200XL and 3200DX Families
PDF  84 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX-FPLC Datasheet(HTML) 28 Page - Actel Corporation

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Inte gra t or Serie s FP GAs: 1 200XL a nd 3200 DX F amilie s
28
Discontinued – v3.0
A122 5XL Timing Cha r ac teristics
( Worst- C a se C omme rc ia l C ond iti on s, V CC = 4.75 V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Logic ModulePropagation Delays1
tPD1
Single Module
2.6
3.0
3.5
5.0
4.2
ns
tCO
Sequential Clk-to-Q
2.6
3.0
3.5
5.0
4.2
ns
tGO
Latch G-to-Q
2.6
3.0
3.5
5.0
4.2
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.6
3.0
3.5
5.0
4.2
ns
Predicted Routing Delays2
tRD1
FO=1 Routing Delay
0.8
0.9
1.1
1.57
1.3
ns
tRD2
FO=2 Routing Delay
1.3
1.4
1.7
2.43
2.0
ns
tRD3
FO=3 Routing Delay
1.7
1.8
2.2
3.15
2.6
ns
tRD4
FO=4 Routing Delay
2.0
2.3
2.7
3.86
3.2
ns
tRD8
FO=8 Routing Delay
3.2
3.5
4.2
6.00
5.0
ns
Sequential Timing Characteristics3,4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.4
0.4
0.5
0.7
0.6
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.8
0.9
1.0
1.4
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
3.2
3.6
4.3
6.1
5.2
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
3.2
3.6
4.3
6.1
5.2
ns
tA
Flip-Flop Clock Input Period
6.5
7.4
8.7
12.4
10.4
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.4
0.4
0.6
0.5
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.4
0.4
0.6
0.5
ns
fMAX
Flip-Flop (Latch) Clock
Frequency
225
200
170
120
115
MHz
Notes:
1.
For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4.
Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing
parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts
(adds) to the internal set-up (hold) time.
5.
VCC = 3.0V for 3.3V specifications.



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