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A32100DX-FPLC Datasheet(PDF) 39 Page - Actel Corporation |
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A32100DX-FPLC Datasheet(HTML) 39 Page - Actel Corporation |
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39 / 84 page ![]() Discontinued – v3.0 39 Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies A128 0XL Timing Cha r ac teristics (continued) (Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C) ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed 3.3V ‘Std’ Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units TTL Output Module Timing1 tDLH Data-to-Pad High 3.8 4.3 5.0 7.1 6.0 ns tDHL Data-to-Pad Low 4.1 4.6 5.4 7.7 6.5 ns tENZH Enable-Pad Z to High 3.8 4.3 5.0 7.1 6.0 ns tENZL Enable-Pad Z to Low 4.1 4.7 5.5 7.7 6.6 ns tENHZ Enable-Pad High to Z 5.4 6.1 7.2 10.3 8.6 ns tENLZ Enable-Pad Low to Z 5.4 6.1 7.2 10.3 8.6 ns tGLH G-to-Pad High 4.2 4.8 5.6 8.0 6.7 ns tGHL G-to-Pad Low 4.7 5.4 6.3 9.0 7.6 ns tLCO I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading 9.8 11.0 13.1 18.7 15.7 ns tACO Array Clock-Out (Pad-to-Pad), 64 Clock Loading 13.9 15.7 18.5 26.4 22.2 ns dTLH Capacitive Loading, Low to High 0.04 0.04 0.05 0.06 0.06 ns/pF dTHL Capacitive Loading, High to Low 0.05 0.06 0.07 0.08 0.08 ns/pF CMOS Output Module Timing1 tDLH Data-to-Pad High 4.8 5.4 6.4 9.1 7.7 ns tDHL Data-to-Pad Low 3.4 3.8 4.5 6.4 5.4 ns tENZH Enable-Pad Z to High 3.8 4.3 5.0 7.1 6.0 ns tENZL Enable-Pad Z to Low 4.1 4.7 5.5 7.9 6.6 ns tENHZ Enable-Pad High to Z 5.4 6.1 7.2 10.3 8.6 ns tENLZ Enable-Pad Low to Z 5.4 6.1 7.2 10.3 8.6 ns tGLH G-to-Pad High 4.2 4.8 5.6 8.0 6.7 ns tGHL G-to-Pad Low 4.7 5.4 6.3 9.0 7.6 ns tLCO I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading 11.6 13.0 15.5 22.2 18.6 ns tACO Array Clock-Out (Pad-to-Pad), 64 Clock Loading 16.4 18.5 21.8 31.2 26.2 ns dTLH Capacitive Loading, Low to High 0.05 0.06 0.07 0.08 0.08 ns/pF dTHL Capacitive Loading, High to Low 0.05 0.05 0.06 0.07 0.07 ns/pF Note: 1. Delays based on 35 pF loading. |
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