Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

A32100DX-FPLC Datasheet(PDF) 47 Page - Actel Corporation

Part # A32100DX-FPLC
Description  Integrator Series FPGAs: 1200XL and 3200DX Families
PDF  84 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX-FPLC Datasheet(HTML) 47 Page - Actel Corporation

Back Button A32100DX-FPLC Datasheet HTML 43Page - Actel Corporation A32100DX-FPLC Datasheet HTML 44Page - Actel Corporation A32100DX-FPLC Datasheet HTML 45Page - Actel Corporation A32100DX-FPLC Datasheet HTML 46Page - Actel Corporation A32100DX-FPLC Datasheet HTML 47Page - Actel Corporation A32100DX-FPLC Datasheet HTML 48Page - Actel Corporation A32100DX-FPLC Datasheet HTML 49Page - Actel Corporation A32100DX-FPLC Datasheet HTML 50Page - Actel Corporation A32100DX-FPLC Datasheet HTML 51Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 47 / 84 page
background image
Discontinued – v3.0
47
Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies
A322 00DX Timing Char act eristics
(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)
‘–3 Speed
‘–2 Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
3.3V ‘Std’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays
Combinatorial Functions
tPD
Internal Array Module Delay
2.0
2.4
2.7
3.2
4.5
3.7
ns
tPDD
Internal Decode Module Delay
2.5
2.9
3.3
3.9
5.6
4.5
ns
Predicted Module Routing Delays
tRD1
FO=1 Routing Delay
1.1
1.35
1.5
1.8
2.6
2.1
ns
tRD2
FO=2 Routing Delay
1.7
2.0
2.2
2.6
3.7
3.0
ns
tRD3
FO=3 Routing Delay
2.1
2.4
2.8
3.3
4.7
3.8
ns
tRD4
FO=4 Routing Delay
2.6
3.0
3.4
4.0
5.7
4.7
ns
tRD5
FO=8 Routing Delay
4.5
5.3
6.0
7.0
10.0
8.2
ns
tRDD
Decode-to-Output Routing Delay
0.6
0.67
0.8
0.9
1.3
1.0
ns
Sequential Timing Characteristics
tCO
Flip-Flop Clock-to-Output
2.3
2.7
3.1
3.6
5.1
4.2
ns
tGO
Latch Gate-to-Output
2.0
2.4
2.7
3.2
4.5
3.7
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.3
0.35
0.4
0.47
0.7
0.55
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset to Output
2.3
2.7
3.1
3.6
5.1
4.2
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.75
0.9
1.0
1.4
1.17
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.1
3.7
4.2
4.9
7.0
5.7
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
4.1
4.9
5.5
6.5
9.2
7.6
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com