LTC4253AIGN-ADJ datasheet(22/32 Pages) LINER

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LTC4253A-ADJ

4253a-adjf

APPLICATIO S I FOR ATIO

TIMING WAVEFORMS

System Power-Up

Figure 8 details the timing waveforms for a typical power-

up sequence in the case where a board is already installed

in the backplane and system power is applied abruptly. At

4253A F08

GATE

START-UP

INITIAL TIMING

VLKO

VGATEL

GND – VEE OR

(–48RTN) – (–48V)

OVL

VIN

TIMER

GATE

SENSE

VOUT

3 4 56

DRAIN

PWRGD1

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

VUVHI

VOVLO

VIN CLEARS VLKO, CHECK UV > VUVHI, OVL < VOVLO, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

VSQTMRL

µA

VSQTMRH

VIH

VTMRH

VACL

VCB

VTMRL

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

µA

VDRNCL

VDRNL

VIN – VGATEH

200

µA + 8 • IDRN

UVL

time point 1, the supply ramps up, together with UV/OV,

VOUT and DRAIN. VIN and the PWRGD signals follow at a

slower rate as set by the VIN bypass capacitor. At time

point 2, VIN exceeds VLKO and the internal logic checks for

UV > VUVHI, OVL < VOVLO, RESET < 0.8V, GATE < VGATEL,

SENSE < VCB, SS < 20 • VOS, and TIMER < VTMRL. When

Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)

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