TMS320C44 datasheet(13/42 Pages) TI

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TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory aliasing

The ’320C44 offers global and local addresses of A0 – A23 and LA0 – LA23, giving an external address reach

of (2 buses)

× (224) = 225 words. Since the internal address span of the ’320C44 is 232 words, reading or writing

to memory outside of the base-address region causes memory aliasing. Figure 2 shows how the memory pages

overlap each other.

External Alias n

External Alias 1

External Alias 2

Local Bus

0x7F00 0000

0x0200 0000

0x02FF FFFF

0x0100 0000

0x7FFFFFFF

0x01FF FFFF

External Alias n

External Alias 1

External Alias 2

Global Bus

0xFF00 0000

0x8200 0000

0x82FF FFFF

0x8100 0000

0xFFFFFFFF

0x81FF FFFF

Base-Address

Region

0x0000 0000

0x00FF FFFF

Base-Address

Region

0x8000 0000

0x80FF FFFF

Figure 2. Memory Alias

central processing unit

The ’320C44 CPU is configured for high-speed internal parallelism for the highest sustained performance. The

key features of the CPU are:

D Eight operations/cycle:

–

40- / 32-bit floating-point / integer multiply

–

40- / 32-bit floating-point / integer ALU operation

–

Two data accesses

–

Two address-register updates

D Floating-point conversion

D Divide and square-root support

D ’C3x and ’C4x assembly-language compatibility

D Byte and halfword accessibility

TMS320C44 Datasheet(PDF) 13 Page - Texas Instruments

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