TMS320C44 datasheet(3/42 Pages) TI

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TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

block diagram (continued)

LD31 – LD0

LA23 – LA0

LDE

LAE

LSTAT3 – LSTAT0

LLOCK

LSTRB0, LSTRB1

LR / W0, LR / W1

LPAGE0, LPAGE1

LRDY0, LRDY1

LCE0, LCE1

DMA Channel 1

DMA Channel 2

DMA Channel 4

DMA Channel 5

DMA Coprocessor

Six DMA Channels

Global

Local

Port Control

Global-Control Register

Time-Period Register

Timer 1

Timer-Counter Register

TCLK1

Global-Control Register

Time-Period Register

Timer 0

Timer-Counter Register

TCLK0

Port-Control Registers

Output

FIFO

Input

FIFO

PAU

COM Port 1

CREQ1

CACK1

CSTRB1

CRDY1

C1D7 – C1D0

Port-Control Registers

Output

FIFO

Input

FIFO

PAU

COM Port 5

CREQ5

CACK5

CSTRB5

CRDY5

C5D7 – C5D0

DDATA Bus

DADDR 1 Bus

DADDR 2 Bus

PADDR Bus

PDATA Bus

COM Port 2

COM Port 4

Four

Communication

Ports†

DMADATA Bus

DMAADDR Bus

MUX

DMA Channel 0

DMA Channel 3

CDIR1

CDIR5

† Communication ports 0 and 3 are not connected.

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