AS8S512K32AP-20SLASHSPACE datasheet(8/14 Pages) AUSTIN

8 / 14 page

SRAM

AS8S512K32

& AS8S512K32A

AS8S512K32 & AS8S512K32A

Rev. 6.0 6/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

7. At any given temperature and voltage condition,

HZCS, is less than tLZCS, and tHZWE is less than tLZWE.

8. WE\ is HIGH for READ cycle.

9. Device is continuously selected. Chip selects and output

enable are held in their active state.

10. Address valid prior to or coincident with latest occurring

chip enable.

11. t

RC= READ cycle time.

12. Chip enable (CS\) and write enable (WE\) can initiate and

terminate a WRITE cycle.

13. I

CC is for 32 bit mode.

NOTES

1. All voltages referenced to V

SS (GND).

2. -2V for pulse width <20ns.

3. ICC is dependent on output loading and cycle rates.

The specified value applies with the outputs

4. This parameter guaranteed but not tested.

5. Test conditions as specified with output loading as

shown in Fig. 1 unless otherwise noted.

6. t

HZCS, tHZOE and tHZWE are specified with CL= 5pF as in Fig. 2.

Transition is measured +/- 200 mV typical from steady state

voltage, allowing for actual tester RC time constant.

RC(MIN)

unloaded, and f=

HZ.

LOW V

CC DATA RETENTION WAVEFORM

LOW POWER CHARACTERISTICS (L Version Only)

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

NOTES

VCC for Retention Data

VDR

VCC = 2V

ICCDR

VCC = 3V

ICCDR

28*

Chip Deselect to Data

Retention Time

tCDR

0ns

Operation Recovery Time

tRC

4, 11

Data Retention Current

All Inputs @ Vcc + 0.2V

or Vss + 0.2V,

CS\ = Vcc + 0.2V

CONDITIONS

123456789012345678

12345

12345678

123456789012345678

12345

12345678

DATA RETENTION MODE

4.5V

DR>2V

tCDR

CS\ 1-4

* -12 and -15 have a 32mA limit.

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