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STM32W108HB Datasheet(PDF) 104 Page - STMicroelectronics

Part # STM32W108HB
Description  High-performance, IEEE 802.15.4 wireless system-on-chip
PDF  179 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32W108HB Datasheet(HTML) 104 Page - STMicroelectronics

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General-purpose timers
STM32W108CB, STM32W108HB
104/179
Doc ID 16252 Rev 2
●
Configure the timer in gated mode by writing TIM_SMS = 101 in the TIMx_SMCR
register. Select TI1 as the input source by writing TIM_TS = 101 in the TIMx_SMCR
register.
●
Enable the counter by writing TIM_CEN = 1 in the TIMx_CR1 register. In gated mode,
the counter does not start if TIM_CEN = 0, regardless of the trigger input level.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The INT_TIMTIF flag in the INT_TIMxFLAG register is set when the
counter starts and when it stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on the TI1 input.
Figure 37.
Control circuit in gated mode
Slave mode: trigger mode
In trigger mode the counter starts in response to an event on a selected input.
In the following example, the up-counter starts in response to a rising edge on the TI2 input:
●
Configure channel 2 to detect rising edges on TI2 Configure the input filter duration. In
this example, no filter is required so TIM_IC2F = 0000. The capture prescaler is not
used for triggering, so it is not configured. The TIM_CC2S bits select the input capture
source only, TIM_CC2S = 01 in the TIMx_CCMR1 register. Write TIM_CC2P = 0 in the
TIMx_CCER register to validate the polarity and detect high level only.
●
Configure the timer in trigger mode by writing TIM_SMS = 110 in the TIMx_SMCR
register. Select TI2 as the input source by writing TIM_TS = 110 in the TIMx_SMCR
register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
INT_TIMTIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on the TI2 input.



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