STM32W108HB datasheet(105/179 Pages) STMICROELECTRONICS

105 / 179 page

STM32W108CB, STM32W108HB

General-purpose timers

Doc ID 16252 Rev 2

105/179

Figure 38.

Control circuit in trigger mode

Slave mode: external clock mode 2 +trigger mode

External clock mode 2 can be used in combination with another slave mode (except external

clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock

input, and another input can be selected as trigger input when operating in reset mode,

gated mode or trigger mode. It is not recommended to select ETR as TRGI through the

TIM_TS bits of TIMx_SMCR register.

In the following example, the up-counter is incremented at each rising edge of the ETR

signal as soon as a rising edge of TI1 occurs:

●

Configure the external trigger input circuit by programming the TIMx_SMCR register as

follows:

–

TIM_ETF = 0000: no filter.

–

TIM_ETPS = 00: prescaler disabled.

–

TIM_ETP = 0: detection of rising edges on ETR and TIM_ECE = 1 to enable the

external clock mode 2.

●

Configure the channel 1 as follows, to detect rising edges on TI:

–

TIM_IC1F = 0000: no filter.

–

The capture prescaler is not used for triggering and does not need to be

configured.

–

TIM_CC1S = 01in the TIMx_CCMR1 register to select only the input capture

source.

–

TIM_CC1P = 0 in the TIMx_CCER register to validate the polarity (and detect

rising edge only).

●

Configure the timer in trigger mode by writing TIM_SMS = 110 in the TIMx_SMCR

A rising edge on TI1 enables the counter and sets the INT_TIMTIF flag. The counter then

counts on ETR rising edges.

The delay between the rising edge of the ETR signal and the actual reset of the counter is

due to the resynchronization circuit on ETRP input.

STM32W108HB Datasheet(PDF) 105 Page - STMicroelectronics

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