STM32W108HB datasheet(145/179 Pages) STMICROELECTRONICS

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STM32W108CB, STM32W108HB

Interrupts

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The NVIC also contains a software-configurable interrupt prioritization mechanism. The

Reset, NMI, and Hard Fault exceptions, in that order, are always the highest priority, and are

not software-configurable. All other exceptions can be assigned a 5-bit priority number, with

low values representing higher priority. If any exceptions have the same software-

configurable priority, then the NVIC uses the hardware-defined priority. The hardware-

defined priority number is the same as the position of the exception in the exception table.

For example, if IRQA and IRQB both fire at the same time and have the same software-

defined priority, the NVIC handles IRQA, with priority number 28, first because it has a

higher hardware priority than IRQB with priority number 29.

The top level interrupts are controlled through five ARM® Cortex-M3 NVIC registers:

INT_CFGSET, INT_CFGCLR, INT_PENDSET, INT_PENDCLR, and INT_ACTIVE. Writing 0

into any bit in any of these five register is ineffectual.

●

INT_CFGSET - Writing 1 to a bit in INT_CFGSET enables that top level interrupt.

●

INT_CFGCLR - Writing 1 to a bit in INT_CFGCLR disables that top level interrupt.

●

INT_PENDSET - Writing 1 to a bit in INT_PENDSET triggers that top level interrupt.

●

INT_PENDCLR - Writing 1 to a bit in INT_PENDCLR clear that top level interrupt.

●

INT_ACTIVE cannot be written to and is used for indicating which interrupts are

currently active.

INT_PENDSET and INT_PENDCLR set and clear a simple latch; INT_CFGSET and

INT_CFGCLR set and clear a mask on the output of the latch. Interrupts may be pended

and cleared at any time, but any pended interrupt will not be taken unless the corresponding

mask (INT_CFGSET) is set, which allows that interrupt to propagate. If an INT_CFGSET bit

is set and the corresponding INT_PENDSET bit is set, then the interrupt will propagate and

be taken. If INT_CFGSET is set after INT_PENDSET is set, then the interrupt will also

propagate and be taken. Interrupt flags (signals) from the top level interrupts are level-

sensitive.

The second-level interrupt registers, which provide control of the second-level Event

Manager peripheral interrupts, are described in Section 10.2: Event manager.

For further information on the NVIC and Cortex-M3 exceptions, refer to the ARM® Cortex-

M3 Technical Reference Manual and the ARM ARMv7-M Architecture Reference Manual.

10.1.1

Non-maskable interrupt (NMI)

The non-maskable interrupt (NMI) is a special case. Despite being one of the 10 standard

ARM® Cortex-M3 NVIC interrupts, it is sourced from the Event Manager like a peripheral

interrupt. The NMI has two second-level sources; failure of the 24 MHz crystal and

watchdog low water mark.

Failure of the 24 MHz crystal: If the STM32W108's main clock, SCLK, is operating from

the 24 MHz crystal and the crystal fails, the STM32W108 detects the failure and

automatically switch to the internal 12 MHz RC clock. When this failure detection and

switch has occurred, the STM32W108 triggers the CLK24M_FAIL second-level

interrupt, which then triggers the NMI.

Watchdog low water mark: If the STM32W108's watchdog is active and the watchdog

counter has not been reset for 1.792 seconds, the watchdog triggers the

WATCHDOG_INT second level interrupt, which then triggers the NMI.

STM32W108HB Datasheet(PDF) 145 Page - STMicroelectronics

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