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STM32W108HB Datasheet(PDF) 149 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 149 Page - STMicroelectronics |
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149 / 179 page  STM32W108CB, STM32W108HB Interrupts Doc ID 16252 Rev 2 149/179 10.3 Nested vectored interrupt controller (NVIC) interrupts 10.3.1 Top-level set interrupts configuration register (INT_CFGSET) Address offset: 0x0100 Reset value: 0x0000 0000 10.3.2 Top-level clear interrupts configuration register (INT_CFGCLR) Address offset: 0x0180 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT_DE BUG rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT_IR QD INT_IR QC INT_IR QB INT_IR QA INT_AD C INT_MA CRX INT_MA CTX INT_MA CTMR INT_SE C INT_SC 2 INT_SC1 INT_SL EEPTM R INT_BB INT_MG MT INT_TIM 2 INT_TIM 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [16] INT_DEBUG: Write 1 to enable debug interrupt. (Writing 0 has no effect.) [15] INT_IRQD: Write 1 to enable IRQD interrupt. (Writing 0 has no effect.) [14] INT_IRQC: Write 1 to enable IRQC interrupt. (Writing 0 has no effect.) [13] INT_IRQB: Write 1 to enable IRQB interrupt. (Writing 0 has no effect.) [12] INT_IRQA: Write 1 to enable IRQA interrupt. (Writing 0 has no effect.) [11] INT_ADC: Write 1 to enable ADC interrupt. (Writing 0 has no effect.) [10] INT_MACRX: Write 1 to enable MAC receive interrupt. (Writing 0 has no effect.) [9] INT_MACTX: Write 1 to enable MAC transmit interrupt. (Writing 0 has no effect.) [8] INT_MACTMR: Write 1 to enable MAC timer interrupt. (Writing 0 has no effect.) [7] INT_SEC: Write 1 to enable security interrupt. (Writing 0 has no effect.) [6] INT_SC2: Write 1 to enable serial controller 2 interrupt. (Writing 0 has no effect.) [5] INT_SC1: Write 1 to enable serial controller 1 interrupt. (Writing 0 has no effect.) [4] INT_SLEEPTMR: Write 1 to enable sleep timer interrupt. (Writing 0 has no effect.) [3] INT_BB: Write 1 to enable baseband interrupt. (Writing 0 has no effect.) [2] INT_MGMT: Write 1 to enable management interrupt. (Writing 0 has no effect.) [1] INT_TIM2: Write 1 to enable timer 2 interrupt. (Writing 0 has no effect.) [0] INT_TIM1: Write 1 to enable timer 1 interrupt. (Writing 0 has no effect.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT_D EBUG |
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