STM32W108HB datasheet(146/179 Pages) STMICROELECTRONICS

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Interrupts

STM32W108CB, STM32W108HB

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Doc ID 16252 Rev 2

10.1.2

Faults

Four of the exceptions in the NVIC are faults: Hard Fault, Memory Fault, Bus Fault, and

Usage Fault. Of these four, three of the faults (Hard Fault, Memory Fault, and Usage Fault)

are all standard ARM® Cortex-M3 exceptions.

The Bus Fault, though, is derived from STM32W108-specific sources. The Bus Fault

sources are recorded in the SCS_AFSR register. Note that it is possible for one access to

set multiple SCS_AFSR bits. Also note that MPU configurations could prevent most of these

bus fault accesses from occurring, with the advantage that illegal writes are made precise

faults. The four bus faults are:

●

WRONGSIZE - Generated by an 8-bit or 16-bit read or write of an APB peripheral

●

PROTECTED - Generated by a user mode (unprivileged) write to a system APB or

AHB peripheral or protected RAM.

●

RESERVED - Generated by a read or write to an address within an APB peripheral's 4

kB block range, but the address is above the last physical register in that block range.

Also generated by a read or write to an address above the top of RAM or flash.

●

MISSED - Generated by a second SCS_AFSR fault. In practice, this bit is not seen

since a second fault also generates a hard fault, and the hard fault preempts the bus

fault.

10.2

Event manager

While the standard ARM® Cortex-M3 Nested Vectored Interrupt Controller provides top-

level interrupts into the CPU, the Event Manager provides second-level interrupts. The

Event Manager takes a large variety of hardware interrupt sources from the peripherals and

merges them into a smaller group of interrupts in the NVIC. Effectively, all second-level

interrupts from a peripheral are "ORed" together into a single interrupt in the NVIC. In

addition, the Event Manager provides missed indicators for the top-level peripheral

interrupts with the register INT_MISS.

STM32W108HB Datasheet(PDF) 146 Page - STMicroelectronics