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AT90SCR100 Datasheet(PDF) 291 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 291 Page - ATMEL Corporation |
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291 / 433 page  291 TPR0327AY–SMS–30Jan09 AT90SCR100 21.5.6 HSSPITDR - HSSPI Transmit Data Register • Bits 7..0 - HSSPITDD7..0: Transmit Data value This register is used only when the DPRAM mode is disabled. The HSSPI Transmit Data register is a write register used for data transmission from the register file to the HSSPI Shift register. Writing to the register initiates data transmission. 21.5.7 HSSPIRDR - HSSPI Received Data Register • Bits 7..0 - HSSPIRDD7..0: Receive Data value This register is used only when the DPRAM mode is disabled. The HSSPI Receive Data register is a read register used for data reception to the register file from the HSSPI Shift register. Reading this register causes the Shift Register holding the first received data to be read. 21.5.8 HSSPIGTR - HSSPI Guard Time Register • Bits 7..0 - HSSPIGTD7..0: Guard Time value The HSSPI Guard Time register value is the number of HSSPI clock cycles to be inserted between characters, in master mode only. 21.5.9 HSSPICNT - HSSPI Byte Count Register • Bits 4..0 - HSSPICNTD4..0 : Number of byte received or to send This register is used only when DPRAM mode is activated. Writing this register specifies the number of bytes to be sent and received for the current received and transmit buffers. Bit 7 6543210 $0000D7 HSSPITDD [7..0] HSSPITDR Read/write WWWWWWWW Initial value 0 0 0 0 0 0 0 0 0x00 Bit 7 6543210 $0000D6 HSSPIRDD [7..0] HSSPIRDR Read/write RRRRRRRR Initial value 0 0 0 0 0 0 0 0 0x00 Bit 7 6543210 $0000D5 HSSPIGTD [7..0] HSSPIGTR Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x00 Bit 7 6543210 $0000D3 - - - HSSPICNTD [4..0] HSSPICNT Read/write R R R R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x00 |
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