AT90SCR100 datasheet(295/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

21.6.2

HSSPIDMAD - HSSPIDMA ADdress registers

• Bits 7..6 - Res: Reserved Bits

These bits are reserved bits in the AT90SCR100 and are always read as zero.

• Bits 13..0 - HSSPIDMAD13..0 : HS SPI DMA Address

These bits represents the 14-bit HSSPIDMA Address.

These two registers set the base address in RAM. This address represents the source of the

data to be sent if the HSSPIDMA controller is configured in the emission mode. It represents the

destination to store the data if the HSSPIDMA controller is configured in the receiving mode.

The initial value corresponds to RAM address $000100.

You can address the whole RAM with this parameter. Values in RAM that must not be dumped,

shall be stored out of the HSSPIDMA RAM accessible range.

When starting a HSSPIDMA operation, the hardware will check if the values of HSSPIDMADH,

HSSPIDMADL and HSSPIDMAB registers does not exceed the specific RAM area ($000100 to

$0010FF). If an error is detected, HSSPIDMACS.DMAERR bit is automatically set (one). A

Supervisor RAM Illegal Access Attempt Violation security interrupt (if not masked) is so trig-

gered. HSSPIDMADH, HSSPIDMADL and HSSPIDMAB registers keep their previous value.

21.6.3

HSSPIDMAB - DMA Amount of Bytes Register

This register is dedicated to the amount of bytes to be transferred during the next HSSPIDMA

operation setting.

• Bit 7..5 - Res : Reserved Bits

This bit is reserved bit in the AT90SCR100 and is always read as zero.

Bit

1413

1211

$0000DE

HSSPIDMAD [13..8]

HSSPIDMADH

$0000DD

HSSPIDMAD [8..0]

HSSPIDMADL

Bit

Read/write

R/W

Initial value

0x01

0x00

After a HSSPIDMA operation, HSSPIDMADH and HSSPIDMADL are set to the

last value reached in RAM and incremented by one. For instance, after a 64-byte

transfer started from base address $000100, HSSPIDMAD equals to $000140

(HSSPIDMADH = $01 and HSSPIDMADL = $40). This feature allows to simplify

registers and bits handlings when several HSSPIDMA operations are to be suc-

cessively performed, which can be the case when getting or sending several

packets.

Note

Bit

6543

$00DF

HSSPIDMAB [4..0]

HSSPIDMAB

Read/write

R/W

Initial value

0x00

AT90SCR100 Datasheet(PDF) 295 Page - ATMEL Corporation

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