AT90SCR100 datasheet(294/433 Pages) ATMEL

294 / 433 page

294

TPR0327AY–SMS–30Jan09

AT90SCR100

• The value in the register HSSPIDMAB is greater than the size of the DPRAM (16bytes) for

the HSSPIDMA operation.

When this bit is set, and if the HSSPI interruptions are enabled, an HSSPI interruption is

generated.

• Bit 1- HSSPIDMADIR: DMA Direction Bit:

This bit is set (one) and cleared (zero) by software.

It indicates the direction of the next HSSPIDMA operation transfer between the RAM memory

and the internal DPRAM of HSSPI block.

• If the bit is set (one), the transfer will be from the RAM memory to the current transmission

DPRAM (emission mode). The empty transmission DPRAM will be automatically selected.

• If the bit is cleared (zero), the transfer will be from the current reception DPRAM to the RAM

memory (receiving mode). The firstly filled DPRAM will be selected before the other (more

recently modified).

• Bit 0 - HSSPIDMAR: DMA Run Bit:

This bit is set (one) by software and cleared (zero) by hardware.

This bit controls the HSSPIDMA operation launching.

It is set (one) by software when a HSSPIDMA operation is to be performed.

It is cleared (zero) by hardware at the end of the operation.

Don’t forget to clear the HSSPIDMACS.DMAERR bit before leaving the interrup-

tion routine to avoid repetitive and endless interruptions.

The software does not need to poll this bit in order to detect the end of the HSSPI-

DMA operation. Indeed, when the HSSPIDMACS.DMAR bit is set by the software,

the AVR is automatically stopped. When the end of the HSSSPIDMA operation is

reached, the AVR then automatically executes the instructions following the set-

ting of the bit HSSPIDMACS.DMAR.

A HSSPIDMA operation can not be interrupted because the CPU is not available

during this time.

Caution

Note

AT90SCR100 Datasheet(PDF) 294 Page - ATMEL Corporation