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AT90SCR100 Datasheet(PDF) 292 Page - ATMEL Corporation

Part # AT90SCR100
Description  8-bit Microcontroller for Smart Card Readers
PDF  433 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90SCR100 Datasheet(HTML) 292 Page - ATMEL Corporation

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292
TPR0327AY–SMS–30Jan09
AT90SCR100
Reading this register gives the amount of data received for the current received buffer (In this
case, the current received buffer means that this buffer received the expected number of data or
had a timeout).
21.5.10
HSSPITIMEOUT - HSSPI Timeout Register
• Bits 15..0 - SPITIMEOUT15..0 : Communication Timeout
This register is used only when DPRAM mode is activated. It specifies the number of clock
cycles before a timeout occurs (bit HSSPIIR.TIMEOUT is set). See “HSSPIIR - HSSPI Interrupt
Register” on page 288. The clock is defined by HSSPICFG.SPICKDIV bits. See “HSSPICFG -
HSSPI Config Register” on page 287.
21.6
HSSPIDMA Controller
The HSSPIDMA controller, implemented on the AT90SCR100, is intended to execute fast trans-
fers between the RAM memory and the internal HSSPI DPRAM. This feature allows the
application software of the AT90SCR100 to manage the exchanges imposed by the SPI com-
munication at high frequency.
The HSSPIDMA is enabled as soon as DPRAM mode is activated (by setting bit
HSSPICFG.DPRAM). One HSSPIDMA operation can transfer up to N bytes in (N+1) AVR
cycles.
Writing HSSPICNT register will internally switch the DPRAM buffers.
Thus, the DMA controller will point to the other DPRAM buffer.
Note
Bit
15
141312
11
10
9
8
$0000D2
SPITIMEOUT[15..8]
HSSPITOH
$0000D1
SPITIMEOUT [7..0]
HSSPITOL
Bit
7
6543
2
1
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
0x00
0
0000
0
0
0
0x00
All the registers described in this section cannot be accessed if the HSSPI module
is not enabled.
Caution
!



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