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AT90SCR100 Datasheet(PDF) 296 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 296 Page - ATMEL Corporation |
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296 / 433 page  296 TPR0327AY–SMS–30Jan09 AT90SCR100 • Bits 4..0 - HSSPIDMAB4..0 : HS SPI DMA Amount of Bytes Bits These bits are the (4..0) bits of the 7-bit HSSPIDMA Amount of Bytes value. When starting a HSSPIDMA operation, the hardware will check if the values of HSSPIDMADH, HSSPIDMADL and HSSPIDMAB registers does not exceed the specific RAM area ($000100 to $0010FF). If an error is detected, HSSPIDMACS.DMAERR bit is automatically set (one). A Supervisor RAM Illegal Access Attempt Violation security interrupt (if not masked) is so trig- gered. HSSPIDMADH, HSSPIDMADL and HSSPIDMAB registers keep their previous value. After a HSSPIDMA operation completion, the value of this register is not reset. The maximum value allowed for HSSPIDMAB is 16. Note |
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