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HT82K76E-L Datasheet(PDF) 31 Page - Holtek Semiconductor Inc

Part # HT82K76E-L
Description  I/O Type 8-Bit OTP MCU
PDF  58 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT82K76E-L Datasheet(HTML) 31 Page - Holtek Semiconductor Inc

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HT82K70E-L/HT82K76E-L
Rev. 1.00
31
September 15, 2009
Bit
Name
Description
7
Z2_WAKEUP
Read only bit.
1: Z2 changed before Z1
0: default
6
Z1_WAKEUP
Read only bit.
1: Z1 changed before Z2
0: default
5
V2_WAKEUP
Read only bit.
1: V2 changed before V1
0: default
4
V1_WAKEUP
Read only bit.
1: V1 changed before V2
0: default
3
SPI_EN
This bit control the shared PIN (SCS, SDI, SDO and SCK) is SPI or GPIO mode
1: SPI mode
0: IO mode (default)
2
SPI_CSEN
1: Enable, this bit is used to enable/disable software CSEN function
0: Disable, SCS define as GPIO (default)
1
CKEG
1: SPI first output the data immediately after the SPI is enable. And SPI output the data in
the falling edge(polarity=0) or rising edge (polarity=1); SPI read data in the in the rising
edge (polarity=0) or falling edge (polarity=1);
0: SPI output the data in the rising edge(polarity=0) or falling edge (polarity=1);
SPI read data in the in the falling edge(polarity=0) or rising edge (polarity=1); (default)
0
SPI_ CPOL
1: clock polarity rising
0: clock polarity falling (default)
Note: The Internal Register bit4~bit7 data will clear to zero after F/W read the register.
Wake-up Status Register
- WSR
Bit
Name
Description
7
6
5
LVD_sel
To Selected low voltage detector level, Bit 7, 6, 5=
000: 1.0V
001: 1.2V
010: 1.4V
011: 2.0V
100: 2.4V
101: 2.7V
110: 3.0V
111: 3.3V
4
LVD_rd_ctrl
To control the DC/DC to check the LVD voltage
1: enable LVD
0: disable LVD (default)
3
Low battery
Flag for battery low signal (error 5%)
1: battery voltage
£ according LVD_sel voltage
0: battery voltage > according LVD_sel voltage
The user should wait at least 20
ms after set LVD_rd_ctrl and then read the corresponding
voltage Low battery signal
2
WDTEN
To control the Watchdog timer
1: enable
0: disable
1
TMR1S
To selected Timer 1 source
1: WDT OSC
0: fSYS/4
Where WDT OSC is selected as TMR1 source. WDT OSC is always enabled.
0
¾
Unimplemented, read as
²0²
Control Register
- CTLR



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